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HT86BXX/HT86BRXX Enhanced Voice 8-Bit MCU
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: 2.2V~5.5V * System clock: 4MHz~8MHz * Crystal and RC system oscillator * 16/20/24 I/O pins * 8K16-bit Program Memory * 1928/3848-bit Data Memory * External interrupt input * Three 8-bit programmable Timers with overflow * External RC oscillator converter * 8 capacitor/resistor sensor input * Watchdog timer function * 8-level subroutine nesting * Low voltage reset function * Integrated voice ROM with various capacities * Power-down function and wake-up feature reduce
power consumption
* Up to 0.5ms instruction cycle with 8MHz system clock
interrupt and 8-stage prescaler
* 12-bit high quality voltage type D/A output * PWM circuit direct audio output
at VDD= 5V
* 63 powerful instructions
General Description
The Voice type series of MCUs are 8-bit high performance microcontrollers which include a voice synthesizer and tone generator. They are designed for applications which require multiple I/Os and sound effects, such as voice and melody. The devices can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. They also include an integrated high quality, voltage type DAC output. The external interrupt can be triggered with falling edges or both falling and rising edges. The devices are excellent solutions for versatile voice and sound effect product applications with their efficient MCU instructions providing the user with programming capability for powerful custom applications. The system frequency can be up to 8MHz at an operating voltage of 2.2V and include a power-down function to reduce power consumption.
Device Types
Devices which have the letter BR within their part number, indicate that they are OTP devices offering the advantages of easy and effective program updates, using the Holtek range of development and programming tools. These devices provide the designer with the means for fast and low-cost product development cycles. Devices which have the letter B within their part number indicate that they are mask version devices. These devices offer a complementary device for applications that are at a mature state in their design process and have high volume and low cost demands. Part numbers including R are OTP devices, all others are mask version devices. Fully pin and functionally compatible with their OTP sister devices, the mask version devices provide the ideal substitute for products which have gone beyond their development cycle and are facing cost-down demands. In this datasheet, for convenience, when describing device functions, only the OTP types are mentioned by name, however the same described functions also apply to the Mask type devices.
Rev. 1.80
1
March 12, 2010
HT86BXX/HT86BRXX
Selection Table
The devices include a comprehensive range of features, with most features common to all devices. The main features distinguishing them are Program Memory and Data Memory capacity, Voice ROM and Voice capacity, I/O count, stack size and package types. The functional differences between the devices are shown in the following table.
Part No. VDD 2.2V~ 5.5V Program Data Memory Memory 4K16 1928 Voice ROM 96K8 Voice Capacity 36sec Timer I/O 8-bit 12 3 16-bit 3/4 3/4 C/R-F DAC 12-bit PWM 3/4 8 Audio Output Stack Package Types 16NSOP, 24SSOP (150/209mil) 24SSOP(209mil), 28SOP, 44QFP 2.2V~ 5.5V HT86B10 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 8K16 1928 192K8 72sec 16 3 3/4 3/4 12-bit O 8 24SSOP (150/209mil), 28SOP, 44QFP 28SOP, 44QFP
HT86B03 HT86BR10
HT86B20 HT86BR30 HT86B30 HT86B40 HT86B50 HT86BR60 HT86B60 HT86B70 HT86B80 HT86B90
8K16
1928
256K8
96sec
16
3
3/4 3/4
3/4 3/4 O O O O O O
12-bit
O O O O O O O O
8
8K16
1928
384K8
144sec
16
3
12-bit
8
28SOP, 44QFP
8K16 8K16
3848 3848
512K8 768K8
192sec 288sec
20 20
3 3
1 1
12-bit 12-bit
8 8
28SOP, 44QFP 28SOP, 44QFP 28SOP
8K16
3848
1024K8
384sec
20
3
1
12-bit
8 28SOP, 44QFP 8 8 8 44/100QFP 44/100QFP 100QFP
8K16 8K16 8K16
3848 3848 3848
1536K8 2048K8 3072K8
576sec 768sec 1152sec
24 24 24
3 3 3
1 1 1
12-bit 12-bit 12-bit
Note: 1. For devices that exist in more than one package formats, the table reflects the situation for the larger package. 2. For the HT86B90, the operating voltage is 2.2V~5.5V at fSYS=4MHz/3.3V~5.5V at fSYS=8MHz. 3. Voice length is estimated by 21K-bit data rate
Block Diagram
W a tc h d o g T im e r S ta c k 8 - b it R IS C MCU C o re Low V o lta g e R eset PW M 8 /1 6 - b it T im e r D /A C o n v e rte rs A n a lo g S w itc h RC O s c illa tio n N o te : " * " T h e H T 8 6 B 0 3 d o e s n o t c o n ta in a P W M fu n c tio n . * W a tc h d o g T im e r O s c illa to r R eset C ir c u it In te rru p t C o n tr o lle r R C /C ry s ta l O s c illa to r
R O M P ro g ra m M e m o ry
R O M D a ta M e m o ry
R A M D a ta M e m o ry
Rev. 1.80
2
March 12, 2010
HT86BXX/HT86BRXX
Pin Assignment
NC 1 2 3 4 5 6 7 8 9 10 11 12 PA7 PA6 VSS 1 2 3 4 5 6 7 8 V D D /IN T RES OSC1 OSC2 VSSA AUD VDDA 16 15 14 13 12 11 10 9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA5 PA4 PA3 PA2 PA1 PA0 PB4 PB5 PB6 24 23 22 21 20 19 18 17 16 15 14 13 NC NC NC VDDA AUD VSSA OSC2 OSC1 RES V D D /IN T VSS PB7 NC PA7 PA6 PA5 PA4 5 6 7 8 9 10 11 12 PA3 PA2 PA1 PA0 PB4 PB5 PB6 4 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 NC NC NC VDDA AUD VSSA OSC2 OSC1 RES IN T VDD VSS NC PA7 PA6 PA5 PA4 5 6 7 8 9 10 11 12 PA3 PA2 PA1 PA0 PB4 PB5 PB6 4 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 NC VSSP VDDP VDDA AUD VSSA OSC2 OSC1 RES V D D /IN T VSS PB7
HT86B03
1 6 N S O P -A
HT86B03 VDDP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PW M1 PW M2 VSSP NC NC NC NC PA7 PA6 PA5 PA4 PA3 PA2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 28 28 28 VDDA AUD VSSA OSC2 OSC1 RES IN T VDD VSS PB2 PB1 PB0 PA0 PA1 SO SO SO SO P -D P -B P -B P -A NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC NC NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC VSS
2 4 S S O P -A
HT86B03
2 4 S S O P -B
H T 8 6 B 1 0 /H T 8 6 B R 1 0 2 4 S S O P -A NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC NC NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2 8 S O P -C 2 8 S O P -B NC NC NC NC NC VDDA AUD VSSA OSC2 OSC1 NC RES IN T VDD
28 27 26 25 24 23 22 21 20 19 18 17 16 15
NC VSSP PW M2 PW M1 VDDP VDDA AUD VSSA OSC2 OSC1 NC RES IN T VDD
NC 1 2 3 4 5 6 7 8 9 NC NC NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC VSS
28 27 26 25 24 23 22 21 20 10 11 12 13 14 19 18 17 16 15
NC NC NC NC VSSP PW M2 PW M1 VDDP OSC2 OSC1 NC RES IN T VDD
HT8 HT8 HT8 HT8
6B 1 6B 2 6B R 6B R
0
0 /H T 8 6 B 3 0 10 30
H T 8 6 B 4 0 /H T 8 6 B 5 0 /H T 8 6 B 6 0 2 8 S O P -A
HT86B 60 HT86B R60
2 8 S O P -B 2 8 S O P -A
HT86B 60 HT86B R60
PW M2 VSSP NC
NC 1 2 3 4 5 6 7 8 9 10 11
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2
44 43 42 41
H T 8 6 B 1 0 /H T 8 6 B 2 0 /H T 8 6 B 3 0 H T 8 6 B R 1 0 /H T 8 6 B R 3 0 4 4 Q F P -B
12 13 14 15 16 17 18 19 20 21 22
NC NC
NC NC
NC
NC
40 39 38 37 36 35 34
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
33 32 31 30 29 28 27 26 25 24 23
PW M VDD VDD AUD VSS OSC OSC NC RES IN T NC A
1 P A NC NC NC NC 2 1 NC NC NC NC NC NC NC NC NC NC NC P P P P P P 2 1 P A A 2 1 P P P P P NC A7 A6 A5 A4 A3 A2 A1 A0 B0 NC NC NC NC B1 2 1
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41
40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
HT86B 4 HT86B 6 HT 44
0 /H 0 /H 86B QFP
T86B50 T86B70 80 -A
12 13 14 15 16 17 18 19 20 21 22
VSS PW M PW M VDD VDD AUD VSS OSC OSC RES IN T
10099 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81 8 7 3 7 4 7 5 7 6 7 7 7 8 7 9 7 10 7 11 7 12 6 13 6 14 6 15 H T 8 6 B 7 0 /H T 8 6 B 8 0 6 16 HT86B 90 6 17 1 0 0 Q F P -A 6 18 6 19 6 20 6 21 6 22 5 23 5 24 5 25 5 26 5 27 5 28 5 29 5 30 5 31 32 33 34 353637 38 39 40 41 42 43 4445 46 4748 49 50 0 9 8 7 6 5 4 3
0 9 8 7 6 5 4 3 2 1
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VS PW PW VD VD 2 1 0 9 8 7 6 5 4 3 2 1 NC SP M2 M1 DP DA
VDD VSS NC NC NC NC PB7 PB6 PB5 PB4 PB3 NC NC NC NC NC NC NC NC NC VDD VSS PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PB3
NC AUD NC VSSA NC NC NC OSC2
OSC1 NC RES IN T VDD VSS PD7 PD6 PD5 PD3 PD2 PD1 PD0 PD4 PB7 PB6 PB5 PB4 PB3 PB2
Rev. 1.80
3
March 12, 2010
HT86BXX/HT86BRXX
Pad Assignment
HT86B03
(0 ,0 ) 25 PA6 1 3 4 5 6 7 8 9 10 PB5 11 PB6 12 13 PB7 VSS 14 VDD 15 IN T 16 RES
17 18 19 20
VDDA 24 23 AUD VSSA OSC2 OSC1
2
PA7
PA5 PA4 PA3 PA2 PA1
22 21
* The IC substrate should be connected to VSS in the PCB layout artwork.
PB4 PA0
Chip size: 19751930 (mm)2
NC
NC
NC
NC
Rev. 1.80
4
March 12, 2010
HT86BXX/HT86BRXX
HT86BR10
PA7 1 34 VSSP
(0 ,0 )
33 PA6 2 3 4 5 6 7 8 9 10 11 12 PB3 PB2 13 14 PB4 PB5 15 16 PB6 PB7 17 VSS 18 19
20 21 22 23
VSSP PW M2 PW M1 VDDP VDDA AUD VSSA 26 25 24 OSC2 OSC1 RES
32 31 30 29 28 27
PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1
* The IC substrate should be connected to VSS in the PCB layout artwork.
IN T VDD
NC
Chip size: 32654010 (mm)2
NC
NC
NC
Rev. 1.80
5
March 12, 2010
HT86BXX/HT86BRXX
HT86B10
33 (0 ,0 ) 32
VSSP PW M2
PA7 1 2 3 4 5 6 7 8 9 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2
31 30 29 28 27 26 25
PW M1 VDDP VDDA AUD VSSA OSC2 OSC1
10 11 12 13 14 15 16 17 18 19 20 21 NC 22 NC 23 NC 24 NC
* The IC substrate should be connected to VSS in the PCB layout artwork.
PB3
PB4
PB5
PB6
Chip size: 19752640 (mm)2
PB7
VSS
VDD
IN T
RES
Rev. 1.80
6
March 12, 2010
HT86BXX/HT86BRXX
HT86BR30
(0 ,0 )
33 PA7 1 2 3 4 5 6 7 8 9 10 11 12 PB3 13 14 PB4 PB5 15 16 PB6 PB7 17 VSS 18 VDD 19 IN T
20 2122 23 24
VSSP PW M2 PW M1 VDDP VDDA AUD VSSA 26 25 OSC2 OSC1
32 31 30 29 28 27
PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2
* The IC substrate should be connected to VSS in the PCB layout artwork.
RES
NC
NC
NC
NC
Chip size: 42804330 (mm)2
Rev. 1.80
7
March 12, 2010
HT86BXX/HT86BRXX
HT86B20/HT86B30
(0 ,0 )
33 32 PA7 1 2 3 4 5 6 7 8 9 10 11 12 PB3 13 PB4 14 PB5 15 PB6 16 PB7 17 VSS 18 VDD 19 IN T 20 RES 212223 24 NC NC NC NC PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 31 30 29 28 27 26 25
VSSP PW M2 PW M1 VDDP VDDA AUD VSSA OSC2 OSC1
Chip size: 19753300 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
8
March 12, 2010
HT86BXX/HT86BRXX
HT86B40
(0 ,0 )
37 36 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 9 10 8 7 6 5 4 3 2 1 35 34 33 32 31 30 29
VSSP PW M2 PW M1 VDDP VDDA AUD VSSA OSC2 OSC1
11 PB2
12 PB3
13 PB4
14 PB5
15 PB6
16 PB7
17 PD4
18 PD5
19 PD6
20 PD7
21 VSS
22 VDD
23 IN T
24 RES
25 2627 28 NC NC NC NC
Chip size: 19753970 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
9
March 12, 2010
HT86BXX/HT86BRXX
HT86BR60
(0 ,0 )
37
VSSP PW M2 PW M1 VDDP VDDA AUD VSSA
30
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2526 2728
36 35 34 33 32 31
29
OSC2 OSC1
* The IC substrate should be connected to VSS in the PCB layout artwork.
IN T VDD VSS PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PB3
Chip size: 42908835 (mm)2
RES
NC
NC
NC
NC
Rev. 1.80
10
March 12, 2010
HT86BXX/HT86BRXX
HT86B50/HT86B60
(0 ,0 )
37 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 1 3 4 5 6 7 9 10 111213141516171819 20 212223 24 RE IN T VD VS PD PD PD PD PB PB PB PB PB PB 3 4 5 6 7 S 2 4 5 6 7 D S 8 2 36 35 34 33 32 31 30 29
VSSP PW M2 PW M1 VDDP VDDA AUD VSSA OSC2 OSC1
25 262728
Chip size: 19755725 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
NC
NC
NC
NC
Rev. 1.80
11
March 12, 2010
HT86BXX/HT86BRXX
HT86B70/HT86B80
(0 ,0 )
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2
1 2 3 4 5 6 7 9 10 11 8 37 36
41 40 39 38
VSSP PW M2 PW M1 VDDP VDDA AUD VSSA
35 12 13141516 17 18 19 20 21 22 2324 2526 27 28 PD4 PB7 PB6 PB5 PB4 PB3 RES IN T VDD VSS PD7 PD6 PD5 PD3 PD2 PD1 PD0
29 30 3132
34 33
OSC2 OSC1
Chip size: 36154940 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
NC
NC
NC
NC
Rev. 1.80
12
March 12, 2010
HT86BXX/HT86BRXX
HT86B90
(0 ,0 )
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2
1 2 3 4 5 6 7 9 10 11 8 37 36 35 12 13141516 17 18 19 20 21 22 2324 2526 27 28 PD4 PB7 PB6 PB5 PB4 PB3 RES IN T VDD VSS PD7 PD6 PD5 PD3 PD2 PD1 PD0
29 30 3132
41 40 39 38
VSSP PW M2 PW M1 VDDP VDDA AUD OSC2 VSSA OSC1
34 33
Chip size: 36206700 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
NC
NC
NC
NC
Rev. 1.80
13
March 12, 2010
HT86BXX/HT86BRXX
Pad Coordinates
HT86B03 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 HT86BR10 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X -1483.900 -1483.900 -1483.900 -1483.900 -1483.900 -1483.900 -1483.900 -1483.900 -1483.900 -1483.900 -1474.850 -1379.850 -1276.850 -1181.850 -1078.850 -983.850 -881.645 Y 1900.000 -838.050 -933.050 -1036.050 -1131.050 -1234.050 -1329.050 -1432.050 -1527.050 -1630.050 -1856.400 -1856.400 -1856.400 -1856.400 -1856.400 -1856.400 -1856.400 Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X -779.500 -682.500 -521.245 -447.245 -373.245 -299.245 1478.900 1478.900 1478.900 1442.800 1442.800 1442.800 1439.405 1442.395 1442.395 1442.395 1468.400 Y -1856.400 -1856.400 -1860.845 -1860.845 -1860.845 -1860.845 -1821.650 -1700.550 -1605.550 -1497.530 -1395.130 -1295.470 -1162.343 -1024.550 -814.050 -683.200 1879.850 X -879.400 -784.400 -839.400 -839.400 -839.400 -839.400 -839.400 -632.350 -537.350 -434.350 -339.350 -236.350 -141.350 Y -236.700 -236.700 -428.200 -523.200 -626.200 -721.200 -824.200 -816.900 -816.900 -816.900 -816.900 -816.900 -816.900 Unit: mm Pad No. 14 15 16 17 18 19 20 21 22 23 24 25 X -46.350 51.150 154.150 294.450 368.450 442.450 516.450 839.390 839.390 839.390 839.390 737.790 Y -816.900 -816.900 -816.900 -833.650 -833.650 -833.650 -833.650 -592.550 -488.250 -321.808 -218.358 -116.308 Unit: mm
Rev. 1.80
14
March 12, 2010
HT86BXX/HT86BRXX
HT86B10 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HT86BR30 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X -1991.400 -1991.400 -1991.400 -1991.400 -1991.400 -1991.400 -1991.400 -1991.400 -1991.400 -1991.400 -1991.400 -1771.750 -1668.750 -1573.750 -1470.750 -1375.750 -1251.695 Y -1030.120 -1133.120 -1228.120 -1331.120 -1426.120 -1529.120 -1624.120 -1727.120 -1822.120 -1925.120 -2020.120 -2016.400 -2016.400 -2016.400 -2016.400 -2016.400 -2016.780 Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X -1152.895 -1055.695 -913.745 -709.506 -635.506 -561.506 -487.506 1984.750 1984.750 1941.835 1941.835 1941.835 1946.850 1946.850 1946.850 1946.850 Y -2016.400 -2016.400 -2016.400 -2015.810 -2015.810 -2015.810 -2015.810 -2016.500 -1921.500 -1711.230 -1586.960 -1487.300 -1363.920 -1233.070 -1022.570 -891.720 X -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -632.150 -537.150 -434.150 -339.150 -236.150 -141.150 Y -189.100 -284.100 -387.100 -482.100 -585.100 -680.100 -783.100 -878.100 -981.100 -1076.100 -1179.100 -1171.900 -1171.900 -1171.900 -1171.900 -1171.900 -1171.900 Unit: mm Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X -45.150 50.850 153.850 294.450 368.450 442.450 516.450 838.940 838.940 802.900 802.900 802.900 792.250 803.900 803.900 803.900 Y -1171.900 -1171.900 -1171.900 -1188.650 -1188.650 -1188.650 -1188.650 -945.650 -843.250 -704.400 -601.500 -504.300 -351.400 -218.050 -7.550 112.000 Unit: mm
Rev. 1.80
15
March 12, 2010
HT86BXX/HT86BRXX
HT86B20/HT86B30 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HT86B40 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 X -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -848.700 -745.700 -650.700 -547.700 -452.700 -349.700 -254.700 -153.500 -50.500 Y -701.930 -804.930 -899.930 -1002.930 -1097.930 -1200.930 -1295.930 -1398.930 -1493.930 -1596.930 -1836.900 -1836.900 -1836.900 -1836.900 -1836.900 -1836.900 -1836.900 -1836.900 -1836.900 Pad No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 X 44.500 149.650 255.250 359.150 462.150 619.850 693.850 767.850 841.850 839.390 839.390 802.900 802.900 802.900 792.350 803.900 803.900 803.900 Y -1836.900 -1836.900 -1836.900 -1836.900 -1836.900 -1853.600 -1853.600 -1853.600 -1853.600 -1551.700 -1449.300 -1311.300 -1207.800 -1103.500 -959.450 -829.350 -618.850 -499.300 X -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -632.150 -537.150 -434.150 -339.150 -236.150 -141.150 Y -519.100 -614.100 -717.100 -812.100 -915.100 -1010.100 -1113.100 -1208.100 -1311.100 -1406.100 -1509.100 -1501.900 -1501.900 -1501.900 -1501.900 -1501.900 -1501.900 Unit: mm Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X -45.150 50.850 153.850 294.450 368.450 442.450 516.450 838.940 838.940 802.900 802.900 802.900 792.250 803.900 803.900 803.900 Y -1501.900 -1501.900 -1501.900 -1518.650 -1518.650 -1518.650 -1518.650 -1275.650 -1173.250 -1034.400 -931.500 -834.300 -681.400 -548.050 -337.550 -218.000 Unit: mm
Rev. 1.80
16
March 12, 2010
HT86BXX/HT86BRXX
HT86BR60 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HT86B50/HT86B60 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 X -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -839.400 -848.700 -745.700 -650.700 -547.700 -452.700 -349.700 -254.700 -153.400 -50.400 Y -1579.430 -1682.430 -1777.430 -1880.430 -1975.430 -2078.430 -2173.430 -2276.430 -2371.430 -2474.430 -2714.400 -2714.400 -2714.400 -2714.400 -2714.400 -2714.400 -2714.400 -2714.400 -2714.400 Pad No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 X 44.600 149.650 255.250 359.150 462.150 619.850 693.850 767.850 841.850 839.390 839.390 802.900 802.900 802.900 792.350 803.900 803.900 803.900 Y -2714.400 -2714.400 -2714.400 -2714.400 -2714.400 -2731.100 -2731.100 -2731.100 -2731.100 -2427.100 -2326.800 -2188.800 -2085.300 -1981.000 -1836.950 -1706.850 -1496.350 -1376.800 X -1996.400 -1996.400 -1996.400 -1996.400 -1996.400 -1996.400 -1996.400 -1996.400 -1996.400 -1996.400 -1996.400 -1750.825 -1655.825 -1552.825 -1457.825 -1354.825 -1259.825 -1152.350 -1049.350 Y -3279.080 -3382.080 -3477.080 -3580.080 -3675.080 -3778.080 -3873.080 -3976.080 -4074.580 -4177.580 -4272.580 -4269.280 -4269.280 -4269.280 -4269.280 -4269.280 -4269.280 -4269.280 -4269.280 Unit: mm Pad No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 X 954.350 853.150 753.150 657.150 515.200 345.100 271.100 197.100 123.100 1991.750 1991.750 1948.850 1948.850 1948.850 1953.850 1953.850 1953.850 1953.850 Y -4269.280 -4269.280 -4268.900 -4268.900 -4268.900 -4268.850 -4268.850 -4268.850 -4268.850 -4269.000 -4174.000 -3963.730 -3839.460 -3739.800 -3616.420 -3485.570 -3275.070 -3144.220 Unit: mm
Rev. 1.80
17
March 12, 2010
HT86BXX/HT86BRXX
HT86B70/HT86B80 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 HT86B90 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 X -1661.900 -1661.900 -1661.900 -1661.900 -1661.900 -1661.900 -1661.900 -1661.900 -1661.900 -1661.900 -1661.900 -1421.755 -1326.755 -1223.755 -1128.755 -1025.755 -930.755 -827.755 -732.755 -629.755 -534.755 Y -2222.900 -2317.900 -2420.900 -2515.900 -2618.900 -2713.900 -2816.900 -2911.900 -3014.900 -3109.900 -3212.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 Pad No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 X -433.555 -330.555 -235.555 -133.355 -35.365 64.640 167.640 329.595 403.595 477.595 551.595 1656.900 1493.095 1573.595 1656.900 1493.095 1621.410 1621.410 1621.410 1621.410 Y -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3201.900 -3207.150 -3207.150 -3207.150 -3207.150 -3204.995 -2859.695 -2967.795 -3109.995 -2749.845 -2654.245 -2520.895 -2310.395 -2190.845 X -1659.400 -1659.400 -1659.400 -1659.400 -1659.400 -1659.400 -1659.400 -1659.400 -1659.400 -1659.400 -1659.400 -1419.255 -1324.255 -1221.255 -1126.255 -1023.255 -928.255 -825.255 -730.255 -627.255 -532.255 Y -1342.900 -1437.900 -1540.900 -1635.900 -1738.900 -1833.900 -1936.900 -2031.900 -2134.900 -2229.900 -2332.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 Unit: mm Pad No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 X -431.055 -328.055 -233.055 -130.855 -32.865 67.140 170.140 332.095 406.095 480.095 554.095 1658.950 1658.950 1576.095 1495.595 1495.595 1623.910 1623.910 1623.910 1623.910 Y -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2321.900 -2327.150 -2327.150 -2327.150 -2327.150 -2324.995 -2229.995 -2087.795 -1979.695 -1869.845 -1774.245 -1640.895 -1430.395 -1310.845 Unit: mm
Rev. 1.80
18
March 12, 2010
HT86BXX/HT86BRXX
Pin Description
HT86B03/HT86B10/HT86B20/HT86B30/HT86BR10/HT86BR30 Pad Name PA0~PA7 I/O I/O Options Wake-up, Pull-high or None Pull-high or None 3/4 3/4 3/4 Description Bidirectional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). Bidirectional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). The HT86B03 device only has PB4~PB7 port pins. Audio output for driving an external transistor or for driving HT82V733 Audio PWM outputs. The HT86B03 has no PWM outputs. Schmitt trigger reset input. Active low.
PB0~PB7 AUD PWM1 PWM2 RES
I/O O O I
INT
I
External interrupt Schmitt trigger input without pull-high resistor. A configuraFalling Edge tion option determines if the interrupt active edge is a falling edge only or both Trigger or a falling and rising edge. Falling edge triggered active on a high to low transiFalling/Rising tion. Rising edge triggered active on a low to high transition. Input voltage is Edge Trigger the same as operating voltage. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC Crystal or RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. 3/4 3/4 3/4 3/4 3/4 3/4 Positive digital power supply Negative digital power supply, ground. Positive DAC circuit power supply Negative DAC circuit power supply, ground. Positive audio PWM circuit power supply Negative audio PWM circuit power supply, ground.
OSC1 OSC2 VDD VSS VDDA VSSA VDDP VSSP
3/4
3/4 3/4 3/4 3/4 3/4 3/4
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors.
Rev. 1.80
19
March 12, 2010
HT86BXX/HT86BRXX
HT86B40/HT86B50/HT86B60/HT86BR60 Pad Name PA0~PA7 I/O I/O Options Wake-up, Pull-high or None Pull-high or None Description Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). Pins PB0~PB7 are pin-shared with C/R-F input pins K0~K7. Bi-directional 4-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). Pins PD4~PD7 are pin-shared with R/F OSC input pins RR, RC and CC. RCOUT: Capacitor or resistor connection pin to RC OSC for input. RR: Oscillation input pin RC: Reference resistor connection pin for output CC: Reference capacitor connection pin for output Audio output for driving an external transistor or for driving HT82V733 Audio PWM outputs Schmitt trigger reset input. Active low.
PB0~PB7/ K0~K7
I/O
PD4/RCOUT PD5/RR PD6/RC PD7/CC
I/O
Pull-high or None
AUD PWM1 PWM2 RES
O O I
3/4 3/4 3/4
INT
I
External interrupt Schmitt trigger input without pull-high resistor. A configuraFalling Edge tion option determines if the interrupt active edge is a falling edge only or both Trigger or a falling and rising edge. Falling edge triggered active on a high to low transiFalling/Rising tion. Rising edge triggered active on a low to high transition. Input voltage is Edge Trigger the same as operating voltage. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. Positive digital power supply Negative digital power supply, ground. Positive DAC circuit power supply Negative DAC circuit power supply, ground. Positive audio PWM circuit power supply Negative audio PWM circuit power supply, ground.
OSC1 OSC2 VDD VSS VDDA VSSA VDDP VSSP
3/4
Crystal or RC
3/4 3/4 3/4 3/4 3/4 3/4
3/4 3/4 3/4 3/4 3/4 3/4
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors.
Rev. 1.80
20
March 12, 2010
HT86BXX/HT86BRXX
HT86B70/HT86B80/HT86B90 Pad Name PA0~PA7 I/O I/O Options Wake-up, Pull-high or None Pull-high or None Description Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). Pins PB0~PB7 are pin-shared with C/R-F input pins K0~K7. Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). Pins PD4~PD7 are pin-shared with R/F OSC input pins RR, RC and CC. RCOUT: Capacitor or resistor connection pin to RC OSC for input. RR: Oscillation input pin RC: Reference resistor connection pin for output CC: Reference capacitor connection pin for output Audio output for driving an external transistor or for driving HT82V733 Audio PWM outputs Schmitt trigger reset input. Active low.
PB0~PB7/ K0~K7
I/O
PD0~PD3 PD4/RCOUT PD5/RR PD6/RC PD7/CC AUD PWM1 PWM2 RES
I/O
Pull-high or None
O O I
3/4 3/4 3/4
INT
I
External interrupt Schmitt trigger input without pull-high resistor. A configuraFalling Edge tion option determines if the interrupt active edge is a falling edge only or both Trigger or a falling and rising edge. Falling edge triggered active on a high to low transiFalling/Rising tion. Rising edge triggered active on a low to high transition. Input voltage is Edge Trigger the same as operating voltage. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. Positive digital power supply Negative digital power supply, ground. Positive DAC circuit power supply Negative DAC circuit power supply, ground. Positive audio PWM circuit power supply Negative audio PWM circuit power supply, ground.
OSC1 OSC2 VDD VSS VDDA VSSA VDDP VSSP
3/4
Crystal or RC
3/4 3/4 3/4 3/4 3/4 3/4
3/4 3/4 3/4 3/4 3/4 3/4
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors.
Absolute Maximum Ratings
Supply Voltage ...........................VSS+2.2V to VSS+5.5V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.80
21
March 12, 2010
HT86BXX/HT86BRXX
D.C. Characteristics
Test Conditions Symbol Parameter VDD Conditions fSYS=4MHz/8MHz VDD Operating Voltage 3/4 fSYS=4MHz for HT86B90 only fSYS=8MHz for HT86B90 only 3V IDD 5V Operating Current 3V 5V ISTB1 3V Standby Current (WDT Off) 5V ISTB2 VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VLVR IOL1 3V Standby Current (WDT On) 5V Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Input Low Voltage for EXT INT Input High Voltage for EXT INT Low Voltage Reset I/O Port Sink Current 5V IOH1 3V I/O Port Source Current 5V IOL2 3V RC and CC Sink Current 5V IOH2 3V RC and CC Source Current 5V IOL3 3V PWM1/PWM2 Sink Current 5V IOH3 3V PWM1/PWM2 Source Current 5V IAUD 3V AUD Source Current 5V RPH 3V Pull-high Resistance 5V 3/4 VOH=0.9VDD VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V No load, fSYS=8MHz, DAC/PWM disable No load, system HALT WDT disable No load, system HALT WDT enable 3/4 3/4 3/4 3/4 3/4 3/4 LVR 2.2V option VOL=0.1VDD No load, fSYS=4MHz, DAC/PWM disable 2.2 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 0 0.7VDD 2.1 4 10 -2 -5 4 10 -2 -5 50 80 -14.5 -26 -1.5 -3 20 10 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 60 30 5.5 5.5 5.5 1.5 5 3 7 1 2 7 10 0.3VDD VDD 0.4VDD VDD 0.3VDD VDD 2.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50 V V V mA mA mA mA mA mA mA mA V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW kW Min. Typ. Max. Unit Ta=25C
Rev. 1.80
22
March 12, 2010
HT86BXX/HT86BRXX
A.C. Characteristics
Symbol fSYS tWDTOSC tRES tSST tLVR tINT tMAT Parameter System Clock (RC OSC, Crystal OSC) Watchdog Oscillator Period 5V External Reset Low Pulse Width System Start-up Timer Period Low Voltage Reset Time Interrupt Pulse Width 3/4 3/4 3/4 3/4 Test Conditions VDD 3/4 3V Conditions 2.2V~5.5V 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 2.2V~5.5V Min. 4 45 32 1 3/4 2 1 3/4 Typ. 3/4 90 65 3/4 1024 3/4 3/4 3/4 Max. 8 180 130 3/4 3/4 3/4 3/4 400 Ta=25C Unit MHz ms ms ms *tSYS ms ms ns
Circumscribe Memory Access 3/4 Time
Note: *tSYS=1/fSYS
Characteristics Curves
HT86BRxx
* R vs. F Chart Characteristics Curves
R v s . F C h a rt
10 F re q u e n c y (M H z ) 8 6 4 2 150 195 R 285 (k W ) 376 445 4 .5 V 3 .0 V
* T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .0 6 1 .0 4 V 1 .0 2 (2 5 C ) V
SC
DD
=3V
DD
=5V
1 .0 0
V
DD
=5V
V
DD
fO
0 .9 8 0 .9 6 0 .9 4 -6 0 -4 0
SC
=3V
fO
-2 0
0
T (C )
20
40
60
80
100
Rev. 1.80
23
March 12, 2010
HT86BXX/HT86BRXX
* V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
10 8
8 M H z /1 5 0 k W
F re q u e n c y (M H z )
6
6 M H z /1 9 5 k W
4 M H z /2 8 5 k W
4 2
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
4 .2 (V )
4 .5
4 .9
5 .2
5 .5
* V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
10 8
8 M H z /1 4 5 k W
F re q u e n c y (M H z )
6 M H z /1 9 0 k W
6
4 M H z /2 7 4 k W
4 2
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
4 .2 (V )
4 .5
4 .9
5 .2
5 .5
HT86Bxx
* R vs. F Chart Characteristics Curves
R v s . F C h a rt
F re q u e n c y (M H z )
8 6 4 2 68 88 R 127 (k W ) 166 200 3 .0 V 4 .5 V
Rev. 1.80
24
March 12, 2010
HT86BXX/HT86BRXX
* T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .0 4 1 .0 2 1 .0 0 (2 5 C )
SC
V
DD
=5V
0 .9 8 0 .9 6 0 .9 4 0 .9 2 -6 0 -4 0 V
V
DD
=5V
V
DD
=3V
fO
SC
DD
=3V
fO
-2 0
0
20
T (C )
40
60
80
100
* V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
8 M H z /6 7 k W
F re q u e n c y (M H z )
8
6 M H z /8 6 k W
6
4 M H z /1 2 5 k W
4 2
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
4 .2 (V )
4 .5
4 .9
5 .2
5 .5
* V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
8 M H z /6 8 k W
F re q u e n c y (M H z )
8
6 M H z /8 8 k W
6
4 M H z /1 2 7 k W
4 2
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
4 .2 (V )
4 .5
4 .9
5 .2
5 .5
Rev. 1.80
25
March 12, 2010
HT86BXX/HT86BRXX
System Architecture
A key factor in the high-performance features of the Holtek range of Voice microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O, voltage type DAC, PWM direct drive output, capacitor/resistor sensor input and external RC oscillator converter with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/ Resonator or RC oscillator is subdivided into four interO s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
nally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
Rev. 1.80
26
March 12, 2010
HT86BXX/HT86BRXX
Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL, that demand a jump to a non-consecutive Program Memory address. Note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m
C o u n te r
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l 8
Program Counter Mode *12 Initial Reset External Interrupt Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow Timer 3 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine *12 #12 *11 #11 *10 #10 *9 #9 S9 *8 #8 S8 0 0 0 0 0 0 *11 0 0 0 0 0 0 *10 0 0 0 0 0 0 *9 0 0 0 0 0 0 *8 0 0 0 0 0 0 *7 0 0 0 0 0 0 *6 0 0 0 0 0 0 *5 0 0 0 0 0 0 *4 0 0 0 0 1 1 *3 0 0 1 1 0 0 *2 0 1 0 1 0 1 *1 0 0 0 0 0 0 *0 0 0 0 0 0 0
Program Counter + 2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
S12 S11 S10
Program Counter Note: *12~*0: Program counter bits S12~S0: Stack register bits #12~#0: Instruction code bits @7~@0: PCL bits The program counter in the HT86B03 is only 12-bits wide therefore the *12 column in the table is not applicable. 27 March 12, 2010
Rev. 1.80
HT86BXX/HT86BRXX
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations ADD, ADDM, ADC, ADCM, * Location 000H
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
* Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
* Location 008H
This internal vector is used by the 8-bit Timer 0. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 00CH
This internal vector is used by the 8-bit Timer1. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 010H
SUB, SUBM, SBC, SBCM, DAA
* Logic operations AND, OR, XOR, ANDM, ORM,
For the HT86B40, HT86B50, HT86B50, HT86B60, HT86BR60, HT86B70, HT86B80, HT86B90 devices, this internal vector is used by the 16-bit Timer2. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 014H
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
This internal vector is used by the 8-bit Timer3. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
HT H T 8 6 B 1 0 /H T 8 6 B R 1 0 H T H T 8 6 B 2 0 /H T 8 6 B 3 0 HT H T86BR 30 HT In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r 0 In te rru p t V e c to r T im e r 1 In te rru p t V e c to r 86B 86B 86B 86B 4 0 /H T 8 6 B 5 0 6 0 /H T 8 6 B R 6 0 7 0 /H T 8 6 B 8 0 90
SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. By using the appropriate programming tools, this Program memory device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming. Organization The program memory stores the program instructions that are to be executed. It also includes data, table and interrupt entries, addressed by the Program Counter along with the table pointer. The program memory size is 819216 bits. Certain locations in the program memory are reserved for special usage. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
000H 004H 008H 00CH 010H 014H 015H FFFH
H T86B03 In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r 0 In te rru p t V e c to r T im e r 1 In te rru p t V e c to r
In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r 0 In te rru p t V e c to r T im e r 1 In te rru p t V e c to r T im e r 2 In te rru p t V e c to r
T im e r 3 In te rru p t V e c to r
T im e r 3 In te rru p t V e c to r
T im e r 3 In te rru p t V e c to r
1 6 b its 1FFFH 1 6 b its 1 6 b its
Program Memory Structure
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Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, table pointers are used to setup the address of the data that is to be accessed from the Program Memory. However, as some devices possess only a low byte table pointer and other devices possess both a high and low byte pointer it should be noted that depending upon which device is used, accessing look-up table data is implemented in slightly different ways. For the devices, there are two Table Pointer Registers known as TBLP and TBHP in which the lower order and higher order address of the look-up data to be retrieved must be respectively first written. Unlike the other devices in which only the low address byte is defined using the TBLP register, the additional TBHP register allows the complete address of the look-up table to be defined and consequently allow table data from any address and any page to be directly accessed. For these devices, after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of Program Memory using the TABRDC [m] instruction or from the last page of the Program Memory using the TABRDL [m] instruction. When either of these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. tempreg1 tempreg2 db db : : a,06h tblp,a : : tempreg1 ? ? The following diagram illustrates the addressing/data flow of the look-up table for the devices:
TBHP TBLP P ro g ra m M e m o ry
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Look-up Table Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the devices. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is 1F00H which refers to the start address of the last page within the Program Memory of the microcontroller. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 1F06H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
; temporary register #1 ; temporary register #2
mov mov
; initialise table pointer - note that this address ; is referenced ; to the last page or present page
tabrdl
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address 1F06H transferred to tempreg1 and TBLH
dec tabrdl
tblp tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address 1F05H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org dc 1F00h ; sets initial address of HT86B60 last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : 29 March 12, 2010
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Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is Instruction TABRDC [m] TABRDL [m] recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Location *12 P12 1 *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *12~*0: Current Program ROM table P12~P8: Write P12~P8 to TBHP pointer register @7~@0: Write @7~@0 to TBLP pointer register For the HT86B03, the table address location is 12-bits, that is from bit 0 to bit 11.
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of RAM Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Organization The Data Memory is subdivided into two banks, known as Bank 0 and Bank 1, all of which are implemented in 8-bit wide RAM. Most of the RAM Data Memory is loHT8 HT8 HT8 HT8
00H 2DH
cated in Bank 0 which is also subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. The length of these sections is dictated by the type of microcontroller chosen. The start address of the RAM Data Memory for all devices is the address 00H, and the last Data Memory address is FFH. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the
HT8 HT8 HT8 HT8
00H S p e c ia l P u r p o s e D a ta M e m o ry 39H
6B0 6B1 6B2 6BR
0 /H T 8 6 B R 1 0 0 /H T 8 6 B 3 0 30
3
6B4 6B6 6B7 6B9 0
0 /H T 8 6 B 5 0 0 /H T 8 6 B R 6 0 0 /H T 8 6 B 8 0
S p e c ia l P u r p o s e D a ta M e m o ry
Bank 1 M e m o ry
40H G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) FFH :U nknow n
40H
G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s )
40H
FFH
B ank0 Bank 1
FFH
RAM Data Memory Structure - Bank 0, Bank1 Note: Most of the RAM Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i instructions with the exception of a few dedicated bits. The RAM Data Memory can also be accessed through the Memory Pointer registers MP0 and MP1. Rev. 1.80 30 March 12, 2010
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SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory, is located in Bank 0, where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H. Although the Special Purpose Data Memory registers are located in Bank 0, they will still be accessible even if the Bank Pointer has selected Bank 1.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH HT8 HT8 HT8 HT8 HT8 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH L H M L 6B1 6BR 6B2 6B3 6BR IA R 0 MP0 IA R 1 MP1 0 0 0 HT8 HT8 HT8 HT8 HT8 HT8 HT8 IA M IA M 6B40 6B50 6B60 6BR60 6B70 6B80 6B90 R0 P0 R1 P1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1 TM R1C PA PAC PB PBC LA LA LA LA LA LA TCH0 TCH0 TCH0 TCH1 TCH1 TCH1 IN T C H TBHP TM R2H TM R2L TM R2C M H M H L L HT8 HT8 HT8 HT8 HT8 HT8 HT8 2E 2F 30 31 32 33 34 35 36 37 38 39 H H H H H H H H H H H H RC T T R AS O M M C CR CCR R4H R4L OCR 6B4 6B5 6B6 6BR 6B7 6B8 6B9 PD PDC 0 0 0 0 0 0 60
10 30 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH L H M L
HT86 IA M IA M
B03 R0 P0 R1 P1
ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1 TM R1C PA PAC PB PBC LA LA LA LA LA LA TC TC TC TC TC TC IN T TB H0 H0 H0 H1 H1 H1 CH HP H M
ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1 TM R1C PA PAC PB PBC LA LA LA LA LA LA TC TC TC TC TC TC IN T TB H0 H0 H0 H1 H1 H1 CH HP H M
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the RAM Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, watchdog, etc., as well as external functions such as I/O data control. The location of these registers within the RAM Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H. Indirect Addressing Register - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together only access data from Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation.
TM R3 TM R3C V O IC E C DAL DAH VOL LATCHD
TM R3 TM R3C V O IC E C DAL DAH VOL LATCHD PW MC PW ML PW MH
TM R3 TM R3C V O IC E C DAL DAH VOL LATCHD PW MC PW ML PW MH
:U nknow n
Special Purpose Data Memory Structure Memory Pointer - MP0, MP1 For all devices, two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0 only, while MP1 and IAR1 are used to access data from both Bank 0 and Bank 1. The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4.
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data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. IAR0 mp0 block loop ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared a,04h block,a a,offset adres1 mp0,a ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address
Bank Pointer - BP The RAM Data Memory is divided into two Banks, known as Bank 0 and Bank 1. With the exception of the BP register, all of the Special Purpose Registers and General Purpose Registers are contained in Bank 0. If data in Bank 0 is to be accessed, then the BP register must be loaded with the value "00", while if data in Bank 1 is to be accessed, then the BP register must be loaded with the value 01. Using Memory Pointer MP0 and Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer. The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within either Bank 0 or Bank 1. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such
b7
as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the
b0 BP0 B a n k P o in te r BP0 0 1 D a ta M e m o ry Bank 0 Bank 1
N o t u s e d , m u s t b e re s e t to "0 "
Bank Pointer - BP
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high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Watchdog Timer Register - WDTS The Watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Register - INTC, INTCH Two 8-bit register, known as the INTC and INTCH registers, controls the operation of both external and internal timer interrupts. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of the external and timer interrupts can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. Note: In situations where other interrupts may require servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine has been entered.
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
b7 TO PDF OV Z AC b0 C
S T A T U S R e g is te r
Ar Ca Au Ze ith m e r r y fla x ilia r y r o fla g O v e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register
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Timer Registers Depending upon which device is selected, all devices contain three or four integrated Timers of either 8-bit or 16-bit size. All devices contain three 8-bit Timers whose associated registers are known as TMR0, TMR1 and TMR3, which is the location where the associated timer's 8-bit value is located. Their associated control registers, known as TMR0C, TMR1C and TMR3C, contain the setup information for these timers. Some devices also contain an additional 16-bit timer whose register pair name is known as TMR2L/TMR2H and is the location where the timer's 16-bit value is located. An associated control register, known as TMR2C, contains the setup information for this timer. Note that all timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PD, etc. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PDC, etc., also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice-versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. Voice ROM Data Address Latch Counter Registers These are the LATCH0H/LATCH0M/LATCH0L, LATCH1H/LATCH1M/LATCH1L and the Voice ROM data registers. The voice ROM data address latch count e r p r o vi d e s t h e h a n d sh a ki n g b e t w e e n t h e microcontroller and the voice ROM, where the voice codes are stored. Eight bits of voice ROM data will be addressed by using the 22-bit address (except for the HT86B03 which has only 18-bits) latch counter, which is composed of LATCH0H/LATCH0M/LATCH0L or LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice ROM data is addressed, several instruction cycles of at least 4us at least, will be required to latch the voice ROM data, after which the microcontroller can read the voice data from LATCHD. Voice Control and Audio output Registers VOICEC, DAL, DAH, VOL The device includes a single 12-bit current type DAC function for driving an external 8W speaker through an external NPN transistor. The programmer must write the voice data to the DAL/DAH registers. Pulse Width Modulator Registers PWMC, PWML, PWMH Each device contains a single 12-bit PWM function for driving an external 8W speaker. The programmer must write the voice data to PWML/PWMH register. Analog Switch Registers - ASCR Some devices, include 8 analog switch lines, which have an associated register, known as ASCR, for their setup and control. External RC Oscillation Converter Registers RCOCCR, RCOCR, TMR4L, TMR4H For the HT86B40/HT86B50/HT86B60/HT86BR60/ HT86B70/ HT86B80/HT86B90 devices, which have two 16-bit programmable timers, the TMR4L and TMR4H registers are for one of the 16-bit timers. The RCOCCR and RCOCR registers are the control registers for the external RC oscillator.
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Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which device or package is chosen, the microcontroller range provides from 16 to 24 bidirectional input/output lines labeled with port names PA, PB, PD, etc. These I/O ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration options and are implemented using a weak PMOS transistor. Note that if the pull-high option is selected, then all I/O pins on that port will be connected to pull-high resistors, individual pins can be selected for pull-high resistor options. Port A Wake-up Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PDC, etc., to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
* Analog Switch
For the HT86B40, HT86B50, HT86B60, HT86BR60, HT86B70, HT86B80 and HT86B90 devices, pins PB0~PB7 are pin-shared with analog switch pins K0 to K7. The choice of which function is used is selected using configuration options and remains fixed after the device is programmed.
* External RC Oscillator Converter
For the HT86B40, HT86B50, HT86B60, HT86BR60, HT86B70, HT86B80 and HT86B90 devices, pins PD4~PD7 are pin-shared with external oscillator converter pins RCOUT, RR, RC and CC. The external RC oscillator converter function is selected via a configuration option and remains fixed after the device is programmed.
* I/O Pin Structures
The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Note also that the specified pins refer to the largest device package, therefore not all pins specified will exist on all devices.
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V C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D W r ite D a ta R e g is te r CK S Q M U X W a k e - u p O p tio n R e a d D a ta R e g is te r S y s te m W a k e -u p PA0~PA7 Q P u ll- H ig h O p tio n
DD
W eak P u ll- u p
PA Input/Output Port
V C o n tr o l B it D a ta B u s D CK S W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it D W r ite D a ta R e g is te r CK S Q Q
M U X
DD
Q Q
P u ll- H ig h O p tio n
W eak P u ll- u p
PB0~PB7 K0~K7
P B 0 D a ta B it K0~K7 M U X R e a d D a ta R e g is te r
A n a lo g S w itc h O p tio n
PB Input/Output Port
V C o n tr o l B it D a ta B u s D CK S W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it D W r ite D a ta R e g is te r CK S Q Q
M U X
DD
Q Q
P u ll- H ig h O p tio n
W eak P u ll- u p
PD0~PD7 R C O U T,R R ,R C ,C C
P D 0 D a ta B it R C O U T,R R ,R C ,C C M U X R e a d D a ta R e g is te r
E x te rn a l R C C o n v e r te r O p tio n
PD Input/Output Port Rev. 1.80 36 March 12, 2010
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Programming Considerations Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC, PDC, etc., are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, PD, etc., are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
MCU series contain either three or four count up timers of either 8 or 16-bit capacity depending upon which device is selected. The provision of an internal prescaler to the clock circuitry of some of the timer gives added range to the timer. There is single type of register related to the Timer. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer. All devices can have the timer clock configured to come from the internal clock source. The accompanying table lists the associated timer register names. HT86B03 HT86B10 HT86BR10 HT86B20 HT86B30 HT86BR30 No. of 8-bit Timers Timer Register Name 3 TMR0 TMR1 TMR3 TMR0C TMR1C TMR3C 3/4 3/4 3/4 HT86B40 HT86B50 HT86B60 HT86BR60 HT86B70 HT86B80 HT86B90 3 TMR0 TMR1 TMR3 TMR0C TMR1C TMR3C 1 TMR2L TMR2H TMR2C
P o rt D a ta
Timer Control Register
W r ite to P o r t R e a d fro m P o rt
Read/Write Timing Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
No. of 16-bit Timers Timer Register Name Timer Control Register
Configuring the Timer Input Clock Source The clock source for the 8-bit timers is the system clock divided by four while the 16-bit timer has a choice of either the system clock or the system clock divided by four. The 8-bit timer clock source is also first divided by the division ratio of which is conditioned by the three lower bits of the associated timer control register.
Timers
The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The devices in the Voice Type
D a ta B u s P r e lo a d R e g is te r R e lo a d
T3PSC 2~T3PSC 0 T1PSC 2~T1PSC 0 T0PSC 2~T0PSC 0 fS
YS
T3TM 1 T1TM 1 T0TM 1
T3TM 0 T1TM 0 T0TM 0
/4
P r e s c a le r (1 /2 ~ 1 /2 5 6 )
T im e r M o d e C o n tr o l T0O N T1O N T3O N
T im e r 8 - B it T im e r
O v e r flo w to In te rru p t
8-bit Timer Structure
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D a ta B u s L o w B y te B u ffe r
T2TM 1 fS
YS
T2TM 0
1 6 - b it P r e lo a d R e g is te r
R e lo a d
/4
YS
fS
T im e r M o d e C o n tr o l T2O N
H ig h B y te
Low
B y te
1 6 - B it T im e r
O v e r flo w to In te rru p t
16-bit Timer Structure - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90
Timer Registers - TMR0, TMR1, TMR2L/TMR2H, TMR3 The timer registers are special function registers located in the special purpose Data Memory and is the place where the actual timer value is stored. All devices contain three 8-bit timers, whose registers are known as TMR0, TMR1 and TMR3. The HT86B40, HT86B50, HT86B60, HT86BR60, HT86B70, HT86B80 and HT86B90 devices also contain an additional single 16-bit timer, which has a pair of registers known as TMR2L and TMR2H. The value in the timer registers increases by one each time an internal clock pulse is received. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timers at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. Note that to achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the Timer Counters are in an OFF condition and data is written to their preload registers, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. Note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account. For devices which have an internal 16-bit Timer, and which therefore have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely TMR2L, the data will only be placed in a low byte buffer
and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely TMR2H, is executed. However, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Registers - TMR0C, TMR1C, TMR2C, TMR3C Each timer has its respective timer control register, known as TMR0C, TMR1C, TMR2C and TMR3C. It is the timer control register together with their corresponding timer registers that control the full operation of the timers. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. Bits 7 and 6 of the Timer Control Register, which are known as the bit pair TM1/TM0 respectively, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TON, depending upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the timer to run, clearing the bit stops the timer. For the 8-bit timers, which have prescalers, bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler.
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b7 TM 1 TM 0 TON PSC2 PSC1 b0 PSC0 T M R 0 C /T M R 1 C /T M R 3 C T im T0 T1 T3 er PSC PSC PSC 0 0 0 0 1 1 1 1 P re s 2T 2T 2T ca 0 1 3 le r PSC PSC PSC 0 0 1 1 0 0 1 1 R a te T 1 T 1 T 1 Se 0P 1P 3P R e g is te r le c SC SC SC 0 1 0 1 0 1 0 1 t 0 0 0 T im e r R a te 1 :2 1 :4 1 :8 1 :1 1 :3 1 :6 1 :1 1 :2 6 2 4 28 56
N o t im p le m e n t e d , r e a d a s " d o n 't c a r e " T im e r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " Op T0 T1 T3 er TM TM TM 0 0 1 1 a tin g M T 1 T 1 T 1 od 0T 1T 3T 0 1 0 1 e S e le c t M0 M0 M0 no no tim no
m od m od erm m od
e a v a ila b le e a v a ila b le ode e a v a ila b le
Timer Control Register - All Devices
b7 TM 1 TM 0 TON b0 TM R2C R e g is te r
N o t im p le m e n te d , r e a d a s " 0 " T im e r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c TM 2TM 1 TM 2TM 0 no 0 0 no 1 0 tim 0 1 1 1 no t m od m od erm m od e a v a ila b le e a v a ila b le ode e a v a ila b le
Timer Control Register - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90 Configuring the Timer The Timer is used to measure fixed time intervals, providing an internal interrupt signal each time the Timer overflows. To do this the Operating Mode Select bit pair in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits Bit7 Bit6 1 0 Prescaler Rate Select bits, which are bits 0~2 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit, which is bit 4 of the Timer Control Register, can be set high to enable the Timer to run. Each time an internal clock cycle occurs, the Timer increments by one. When it is full and overflows, an interrupt signal is generated and the Timer will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero.
The internal clock, fSYS, is used as the Timer clock. However, this clock source is further divided by a prescaler, the value of which is determined by the
P r e s c a le r O u tp u t In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+1
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Prescaler All of the 8-bit timers possess a prescaler. Bits 0~2 of their associated timer control register, define the pre-scaling stages of the internal clock source of the Timer. The Timer overflow signal can be used to generate signals for the Timer interrupt. Programming Considerations The internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. When the Timer is read, the clock is blocked to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialized before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control register. Timer Program Example The following example program section is based on the HT86B40, HT86B50, HT86B60, HT86BR60, HT86B70, HT86B80 and HT86B90 devices, which contain a single internal 16-bit timer. Programming the timer for other devices is conducted in a very similar way. The program shows how the timer registers are setup along with how the interrupts are enabled and managed. Points to note in the example are how, for the 16-bit timer, the low byte must be written first, this is because the 16-bit data will only be written into the actual timer register when the high byte is loaded. Also note how the timer is turned on by setting bit 4 of the respective timer control register. The timer can be turned off in a similar way by clearing the same bit. This example program sets the timer to be in the timer mode which uses the internal system clock as their clock source.
#include HT86B40.inc jmp begin : org 04h ; external interrupt vectors reti org 08h reti org 0Ch reti org 10h ; timer 2 interrupt vector jmp tmr2int ; jump here when timer 2 overflows org 14h reti : ; internal timer 2 interrupt routine tmr2int: : ; timer 2 main program placed here : reti : begin: ; setup timer 2 registers mov a,09bh ; setup timer 2 low byte mov tmr2l,a ; low byte must be setup before high byte mov a,0e8h ; setup timer 2 high byte mov tmr2h,a ; setup timer 2 high byte mov a,090h ; setup timer 2 control register mov tmr2c,a ; setup timer mode ; setup interrupt register mov a,01h ; enable master interrupt mov intc,a mov a,01h ; enable timer 2 interrupt mov intch,a :
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer requires microcontroller attention, their corresponding interrupt will enforce a temporary susp e n s io n o f t h e m a i n pr o g r am al l ow i n g t h e microcontroller to direct attention to their respective needs. Each device contains a single external interrupt and three or four internal timer interrupt functions. The external interrupt is controlled by the action of the external INT pin, while the internal interrupt is controlled by the relevant Timer overflow. Interrupt Register Overall interrupt control, which means interrupt enabling and flag setting, is controlled using two registers, known as INTC and INTCH, which are located in the Data Memory. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A timer overflow or the external interrupt line being pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the
b7 T1F T0F E IF ET1I ET0I EEI b0 EMI IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le E x te r n a l In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 0 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 1 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 0 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 1 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will take program execution to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
Interrupt Control Register
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b7 T3F T2F ET3I b0 ET2I IN T C H R e g is te r T im e r 2 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 3 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le N o im p le m e n te d , r e a d a s " 0 " T im e r 2 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 3 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
INTCH Register
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e E x te rn a l In te rru p t R e q u e s t F la g E IF T im e r 0 In te r r u p t R e q u e s t F la g T 0 F T im e r 1 In te r r u p t R e q u e s t F la g T 1 F T im e r 3 In te r r u p t R e q u e s t F la g T 3 F EEI
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h
ET0I In te rru p t P o llin g
ET1I
ET3I
Low
Interrupt Structure - HT86B03/HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e E x te rn a l In te rru p t R e q u e s t F la g E IF T im e r 0 In te r r u p t R e q u e s t F la g T 0 F T im e r 1 In te r r u p t R e q u e s t F la g T 1 F T im e r 2 In te r r u p t R e q u e s t F la g T 2 F T im e r 3 In te r r u p t R e q u e s t F la g T 3 F EEI
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h
ET0I
ET1I
In te rru p t P o llin g
ET2I
ET3I
Low
Interrupt Structure - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90
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Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the accompanying table shows the priority that is applied. HT86B03/HT86B10 HT86BR10/HT86B20 HT86B30/HT86BR30 Priority 1 2 3 3/4 4 HT86B40/HT86B50/HT86B60 HT86BR60/HT86B70/HT86B80 HT86B90 Priority 1 2 3 4 5
Interrupt Source
Interrupt Vector
External Interrupt Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow Timer 3 Overflow
04H 08H 0CH 10H 14H
In cases where both external and timer interrupts are enabled and where an external and timer interrupt occur simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the INTC and INTCH registers can prevent simultaneous occurrences. External Interrupt Each device contains a single external interrupt function controlled by the external pin, INT. For an external interrupt to occur, the corresponding external interrupt enable bit must be first set. This is bit 1 of the INTC register and known as EEI. An external interrupt is triggered by an external edge transition on the external interrupt pin INT, after which the related interrupt request flag, EIF, which is bit 4 of INTC, will be set. A configuration option exists for the external interrupt pin to determine the type of external edge transition which will trigger an external interrupt. There are two options available, a low going edge or both high and low going edges. When the master interrupt and external interrupt bits are enabled, the stack is not full and an active edge transition, as setup in the configuration options, occurs on the INT pin, a subroutine call to the corresponding external interrupt vector, which is located at 04H, will occur. After entering the interrupt execution routine, the corresponding interrupt request flag, EIF, will be reset and the EMI bit will be cleared to disable other interrupts. Timer Interrupt For a timer generated interrupt to occur, the corresponding timer interrupt enable bit must be first set. Each device contains three 8-bit timers whose corresponding interrupt enable bits are known as ET0I, ET1I and ET3I and are located in the INTC and INTCH registers. Each timer also has a corresponding timer interrupt request flag, which are known as T0F, T1F and T3F, also located
in the INTC and INTCH registers. Some devices also contain a 16-bit timer, which has a corresponding timer interrupt enable bit, ET2I, and a corresponding timer request flag, T2F, which are contained in the INTCH register. When the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overflows a subroutine call to the corresponding timer interrupt vector will occur. The corresponding Program Memory vector locations for Timer 0, Timer1, Timer 2 and Timer 3 are 08H, 0CH, 10H and 14H. After entering the interrupt execution routine, the corresponding interrupt request flags, T0F, T1F, T2F or T3F will be reset and the EMI bit will be cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC or INTCH register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES
10kW
VDD
0 .1 m F VSS
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be
Enhanced Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
tR
STD
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* Low Voltage Reset - LVR
Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 1 0 u u 1 RESET Conditions RES reset during power-on RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
1
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Timer Prescaler Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting All Timer will be turned off The Timer Prescaler will be cleared
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
tR
S S T T im e - o u t In te rn a l R e s e t
STD
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type.
WDT Time-out Reset during Power Down Timing Chart
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HT86B03 Register MP0 MP1 ACC PCL TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC TMR3 TMR3C INTCH TBHP DAL DAH VOL VOICEC LATCH0H LATCH0M LATCH0L LATCH1H LATCH1M LATCH1L LATCHD Reset (Power-on) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111
--00 0000
WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 1u uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 ---1111 ---0000 0000 00-0 1000
--0- --0-
RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 01 uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 ---1111 ---0000 0000 00-0 1000
--0- --0-
WDT Time-out from HALT uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu ---uuuu ---uuuu uuuu uu-u uuuu
--u- --u-
uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 ---1111 ---0000 0000 00-0 1000
--0- --0-
-000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 ---1111 ---0000 0000 00-0 1000
--0- --0-
0000 0000 0000 ---0000 0000 000- 0000 ---0 -000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
uuuu uuuu uuuu ---uuuu uuuu 000- ------0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu 000- ------0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu 000- ------0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu uuu- ------u -uuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note: u stands for unchanged x stands for unknown - stands for undefined
Rev. 1.80
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March 12, 2010
HT86BXX/HT86BRXX
HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30 Register MP0 MP1 ACC PCL TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC TMR3 TMR3C INTCH TBHP DAL DAH VOL VOICEC LATCH0H LATCH0M LATCH0L LATCH1H LATCH1M LATCH1L LATCHD PWMC PWML PWMH Reset (Power-on) xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0111
--00 xxxx
WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 1u uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000
--0- --0-
RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 01 uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000
--0- --0-
WDT Time-out from HALT uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu
--u- --u-
uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000
--0- --0-
-000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000
--0- --0-
xxxx xxxx xxxx ---xxxx xxxx xxx- xxxx ---0 -00xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0--- 0--0 xxxx ---xxxx xxxx
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0--- 0--0 uuuu ---uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0--- 0--0 uuuu ---uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0--- 0--0 uuuu ---uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---u -uuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- u--u uuuu ---uuuu uuuu
Note: u stands for unchanged x stands for unknown - stands for undefined
Rev. 1.80
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March 12, 2010
HT86BXX/HT86BRXX
HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90 Register MP0 MP1 BP ACC PCL TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PD PDC TMR2H TMR2L TMR2C TMR3 TMR3C INTCH TBHP DAL DAH VOL VOICEC LATCH0H LATCH0M LATCH0L LATCH1H LATCH1M LATCH1L LATCHD Reset (Power-on) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0111
--00 xxxx
WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 1u uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 00-0 ---0000 0000 00-0 1000
--00 --00
RES Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 01 uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 00-0 ---0000 0000 00-0 1000
--00 --00
WDT Time-out from HALT uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u ---uuuu uuuu uu-u uuuu
--uu --uu
uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 00-0 ---0000 0000 00-0 1000
--00 --00
-000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 00-0 ---0000 0000 00-0 1000
--00 --00
xxxx xxxx xxxx ---xxxx xxxx xxx- xxxx ---0 -00xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---0 -00uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
uuuu uuuu uuuu ---uuuu uuuu uuu- uuuu ---u -uuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Rev. 1.80
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March 12, 2010
HT86BXX/HT86BRXX
Register PWMC PWML PWMH ASCR RCOCCR TMR4H TMR4L RCOCR Reset (Power-on) 0--- 0--0 xxxx ---xxxx xxxx
---- 1111
WDT Time-out RES Reset (Normal Operation) (Normal Operation) 0--- 0--0 uuuu ---uuuu uuuu
---- 1111
RES Reset (HALT) 0--- 0--0 uuuu ---uuuu uuuu
---- 1111
WDT Time-out from HALT u--- u--u uuuu ---uuuu uuuu
---- uuuu
0--- 0--0 uuuu ---uuuu uuuu
---- 1111
0010 ---xxxx xxxx xxxx xxxx 1xxx --00
0010 ---xxxx xxxx xxxx xxxx 1xxx --00
0010 ---xxxx xxxx xxxx xxxx 1xxx --00
0010 ---xxxx xxxx xxxx xxxx 1xxx --00
uuuu ---uuuu uuuu uuuu uuuu uuuu --uu
Note: u stands for unchanged x stands for unknown - stands for undefined
Rev. 1.80
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March 12, 2010
HT86BXX/HT86BRXX
Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. Two types of system clocks can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options. The two methods of generating the system clock are:
* External crystal/resonator oscillator * External RC oscillator
External RC Oscillator Using the external system RC oscillator requires that a resistorco. The mask MCU value between 60kW and 130kW, the OTP MCU value between 150kW and 300kW. They connected between OSC1 and VSS. The generated system clock divided by 4 will be provided on OSC2 as an output which can be used for external synchronization purposes. Note that as the OSC2 output is an NMOS open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. Note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation.
OSC1 R fS
YS OSC
One of these two methods must be selected using the configuration options. More information regarding the oscillator is located in Application Note HA0075E on the Holtek website. External Crystal/Resonator Oscillator The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation
C1 Rp In te r n a l O s c illa to r C ir c u it
/4 N M O S O p e n D r a in
OSC2
OSC1 Rf Ca
External RC Oscillator
Watchdog Timer Oscillator
Cb C2 OSC2 T o in te r n a l c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to assist with oscillation start up. Internal Ca, Cb, Rf Typical Values @ 5V, 25C Ca 11~13pF Cb 13~15pF Rf 800kW
The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option.
Oscillator Internal Component Values
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HT86BXX/HT86BRXX
Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the HALT Mode or Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the Watchdog Timer internal oscillator. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/Os, which are setup as
Rev. 1.80
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March 12, 2010
HT86BXX/HT86BRXX
No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended. source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be noted that when the system enters the Power Down Mode, as the system clock is stopped, then the WDT clock source will also be stopped. Therefore the WDT will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate in noisy environments, using the internal WDT oscillator is therefore the recommended choice. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT and the WDT prescaler. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR WDT1 is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the WDT. Similarly, after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT oscillator, or the instruction clock which is the system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. The internal WDT oscillator has an approximate period of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal period of 17ms. Note that this period can vary with VDD, temperature and process variations. For longer WDT time-out periods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With WS0, WS1 and WS2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s. A configuration option can select the instruction clock, which is the system clock divided by 4, as the WDT clock
b7 W S2 W S1
b0 W S0 W D T S R e g is te r W D T p r e s c a le r r a te s e le c t W DTR W S0 W S1 W S2 1 :1 0 0 0 1 :2 1 0 0 1 :4 0 1 0 1 :8 1 1 0 1 :1 0 0 1 1 :3 1 0 1 1 :6 0 1 1 1 :1 1 1 1 2 4 N otused a te
6 28
Watchdog Timer Register
Rev. 1.80
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HT86BXX/HT86BRXX
C L R W D T 1 F la g C L R W D T 2 F la g 1 o r 2 In s tr u c tio n s fS
YS
C le a r W D T T y p e C o n fig u r a tio n O p tio n CLR W D T C lo c k S o u r c e C o n fig u r a tio n O p tio n 8 - b it C o u n te r ( 2 5 6 )
/4
CLR 7 - b it P r e s c a le r
W D T O s c illa to r W D T C lo c k S o u r c e
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
Voice Output
Voice Control The voice control register controls the voice ROM circuit and the DAC circuit and selects the Voice ROM latch counter. If the DAC circuit is not enabled, any DAH/DAL outputs will be invalid. Writing a 1 to the DAC bit will enable the enable DAC circuit, while writing a 0 to the DAC bit will disable the DAC circuit. If the voice ROM circuit is not enabled, then voice ROM data cannot be accessed. Writing a 1 to the VROMC bit will enable the voice ROM circuit, while writing a 0 to the VROMC bit is will disable the voice ROM circuit. The LATCH bit determines which voice ROM address latch counter will be used as the voice ROM address latch counter. Audio Output and Volume Control - DAL, DAH, VOL The audio output is 12-bits wide whose highest 8-bits are written into the DAH register and whose lowest four bits are written into the highest four bits of the DAL register. Bits 0~3 of the DAL register are always read as zero. There are 8 levels of volume which are setup using the VOL register. Only the highest 3-bits of this register are used for volume control, the other bits are not used and read as zero. Voice ROM Data Address Latch Counter The Voice ROM address is 22-bits wide (except for the HT86B03 which has only 10-bits) and therefore requires
b7 LATCHC VROMC DAC b0 V O IC E C R e g is te r N o t im p le m e n te d , r e a d a s " 0 " D A C E n a b le 1 : e n a b le 0 : d is a b le V o ic e R O M 1 : e n a b le 0 : d is a b le E n a b le
three registers to store the address. There are two sets of three registers to store this address, which are LATCH0H/LATCH0M/LATCH0L and LATCH1H/ LATCH1M/LATCH1L. The 22-bit address (except for the HT86B03 which has only 10-bits) stored in one set of these three registers is used to access the 8-bit voice code data in the Voice ROM. After the 8-bit Voice ROM data is addressed, a few instruction cycles, of at least 4us duration, are needed to latch the Voice ROM data. After this the microcontroller can read the voice data from the LATCHD register.
b7 D3 D2 D1 D0 b0 D A L R e g is te r N o t u s e d , re a d a s "0 " A u d io o u tp u t
D ig ita l to A n a lo g D a ta L o w
b7 D11 D10 D9 D8 D7 D6 D5 b0 D4
R e g is te r
R e g is te r
DAH
A u d io o u tp u t
D ig ita l to A n a lo g D a ta H ig h R e g is te r
b7
VO L2VO L1VO L0
b0 V O L R e g is te r U sed by P W M o u tp u t N o t u s e d , re a d a s "0 " D A v o lu m e c o n tr o l d a ta
V o lu m e C o n tr o l R e g is te r
N o t im p le m e n te d , r e a d a s " 0 " V o ic e R O M C o u n te r S e le c t 1 : A d d re s s L a tc h 1 0 : A d d re s s L a tc h 0 N o t im p le m e n te d , r e a d a s " 0 "
VOICE Control Register Rev. 1.80 53 March 12, 2010
HT86BXX/HT86BRXX
Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0 Set [26H].2 ; Enable voice ROM circuit mov A, 07H ; mov LATCH0L, A ; Set LATCH0L to 07H mov A, 00H ; mov LATCH0M, A ; Set LATCH0M to 00H mov A, 00H ; mov LATCH0H, A ; Set LATCH0H to 00H call Delay ; Delay a short period of time mov A, LATCHD ; Get voice data at 000007H
Pulse Width Modulation Output
All device include a single 12-bit PWM function. The PWM output is provided on two complimentary outputs on the PWM1 and PWM2 pins. These two pins can directly drive a piezo buzzer or an 8 ohm speaker without requiring any external components. The PWM1 output can also be used alone to drive a piezo buzzer or an 8 ohm speaker without requiring external components. When the single PWM1 output is chosen, which is achieved by setting the Single_PWM bit in the PWMC register. The PWM output will initially be at a low level, and if stopped will also return to a low level. If the PWMCC bit changes from low to high then the PWM function will start and latch new data. If the data is not updated then the old value will remain. If the PWMCC bit changes from high to low, at the end of the duty cycle, the PWM output will stop.
PW M1 PW M2 0 .0 1 m F * 0 .0 1 m F * S peaker
N o te : " * " F o r r e d u c in g th e d ig ita l n o is e th a t P W M m a y c a u s e , c a n c o n s id e r in c r e m e n t c a p a c ito r s .
b7 P3 P2 P1 P0
b0 P W M L R e g is te r N o t u s e d , re a d a s "0 " PW M o u tp u t
P u ls e W id th M o d u la to r D a ta L o w
b7 P11 P10 P9 P8 P7 P6 P5 b0 P4 PW MH PW M
R e g is te r
R e g is te r
o u tp u t
P u ls e W id th M o d u la to r D a ta H ig h R e g is te r
b7 VO L6 VO L5 VO L4
b0 VO L3 V O L R e g is te r P W M v o lu m e c o n tr o l d a VO L6 VO L5 VO L4 V 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 0 x x 1 N o t u s e d , re a d a s "0 " U s e d b y D A o u tp u t ta O L3 1 0 1 0 1 0 1 x
PW M PW M PW M PW M PW M PW M PW M PW M
v o lu v o lu v o lu v o lu v o lu v o lu v o lu v o lu
m e le m e le m e le m e le m e le m e le m e le m e le
vel vel vel vel vel vel vel vel 7
1 fo r th e m in im u m 2 3 4 5 6 8 fo r th e m a x im u m
v o lu m e
v o lu m e
Volume Control Register
b7 S in g le _ P W M
b0 PW MCC PW MC R e g is te r P W M E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s z e r o S in g le P W M O u tp u t 1 : s in g le o u tp u t 0 : d u a l o u tp u ts N o t im p le m e n te d , r e a d a s z e r o
Pulse Width Modulator Control Register Rev. 1.80 54 March 12, 2010
HT86BXX/HT86BRXX
External RC Oscillation Converter
An external RC oscillation converter is implemented in certain devices and is a function which allows analog switch functions to be implemented. When used in conjunction with the Analog Switch function up to eight C/R-F can be implemented. External RC Oscillation Converter Operation The RC oscillation converter is composed of two 16-bit count-up programmable timers. One is Timer 2, described in the Timer section and the other is an additional counter known as Timer 4. The RC oscillation converter is enabled when the RCO bit, which is bit 1 of the RCOCR register, is set high. The RC oscillation converter will then be composed of four registers, TMR2L, TMR2H, TMR4L and TMR4H. The Timer 2 clock source comes from the system clock or from the system clock/4, the choice of which is determined by bits in the RCOCCR register. The RC oscillation converter Timer 4 clock source comes from an external RC oscillator. As the oscillation frequency is dependent upon external capacitance and resistance values, it can therefore be used to detect the increased capacitance of a analog switch pad. There are six registers related to the RC oscillation converter. These are, TMR2H, TMR2L, RCOCCR, TMR4H,
b7 RCOM2 RCOM1 RCOM0
RCOCON
TMR4L and RCOCR. The internal timer clock is the input clock source for TMR2H and TMR2L, while the external RC oscillator is the clock source input to TMR4H and TMR4L. The OVB bit, which is bit 0 of the RCOCR register, decides whether the timer interrupt is sourced from either the Timer 2 overflows or Timer 4 overflow. When a timer overflow occurs, the T2F bit is set and an external RC oscillation converter interrupt occurs. When the RC oscillation converter Timer 2 or Timer 4 overflows, the RCOCON bit is automatically reset to zero and stops counting. The resistor and capacitor form an oscillation circuit and input to TMR4H and TMR4L. The RCOM0, RCOM1 and RCOM2 bits of RCOCCR define the clock source of Timer 2. When the RCOCON bit, which is bit 4 of the RCOCCR register, is set high, Timer 2 and Timer 4 will start counting until Timer 2 or Timer 4 overflows. Now the timer counter will generate an interrupt request flag which is bit T2F, bit 4 of the INTCH register. Both Timer 2 and Timer 4 will then stop counting and the RCOCON bit will automatically be reset to "0" at the same time. Note that if the RCOCON bit is high, the TMR2H, TMR2L, TMR4H and TMR4L registers cannot be read or written to.
b0 RCOCCR R e g is te r U n d e fin e d , r e a d a s z e r o R C O s c illa to r C o n v e r te r E n a b le 1 : E n a b le 0 : D is a b le T im e r 2 C lo c k S o u r c e S e le c t RCOM2 RCOM1 RCOM0 0 0 0 0 0 1 0 1 0 : : : 1 1 1
fS Y S fS Y S /4 : : U n d e fin e d
RCOCCR Register
b7
RCO
b0 OVB
RCOCR
R e g is te r
In te r r u p t S o u r c e S e le c t 1 : T im e r 4 o v e r flo w 0 : T im e r 2 o v e r flo w R C C o n v e rte r M o d e 1 : E n a b le 0 : D is a b le U n d e fin e d , r e a d a s z e r o
RCOCR Register
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HT86BXX/HT86BRXX
RCOMO fS fS
YS
B it
YS
/4
C lo c k S e le c t
O VB=0 T im e r 2 RCOCON T im e r 4 E x te rn a l R C O s c illa tio n C o n v e r te r In te r r u p t
O VB=1 R esetR C O C O N
RC
OSC
O u tp u t
Programming Considerations As the 16-bit Timers have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte registers, namely TMR2L or TMR4L, the data will only be placed into a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely TMR2H or TMR4H, is executed. However, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. At the same time
the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register.
Program Example External RC oscillation converter mode example program - Timer 2 overflow: clr RCOCCR mov a, 00000010b ; Enable External RC oscillation mode and set Timer 2 ; overflow interrupt mov RCOCR,a clr intch.4 ; Clear External RC Oscillation Converter interrupt ; request flag mov a, low (65536-1000); Give timer 2 initial value mov Tmr2l, a ; Timer 2 count 1000 time and then overflow mov a, high (65536-1000) mov Tmr2h, a mov a, 00h ; Give timer 4 initial value mov Tmr4l, a mov a, 00h mov Tmr4h, a mov a, 00110000b ; Timer 2 clock source=fSYS/4 and timer on mov RCOCCR, a p10: clr Wdt snz intch.4 ; Polling External RC Oscillation Converter interrupt ; request flag jmp p10 clr intch.4 ; Clear External RC Oscillation Converter interrupt ; request flag ; Program continue
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HT86BXX/HT86BRXX
Analog Switch
There are 8 analog switch lines in the microcontroller, labeled as K0 ~ K7, and the Analog Switch control register, which is mapped to the data memory by option. All of these Analog Switch lines can be used together with the external RC Oscillation Converter for C/R-F input keys.
b7
b0 ASON3ASON2ASON1ASON0
ASCR
R e g is te r ASON0 0 1 0 1 0 1 0 1 X
A n a lo g S w itc h S e le c t ASON3 ASON2 ASON1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 0 1 X 1 X U n d e fin e d , r e a d a s z e r o
K0o K1o K2o K3o K4o K5o K6o K7o A ll o
n,o n,o n,o n,o n,o n,o n,o n,o ff, O
th e th e th e th e th e th e th e th e SC
rs o rs o rs o rs o rs o rs o rs o rs o o ff
ff ff ff ff ff ff ff ff
Analog Switch Control Register - ASCR
ASON
K0 K1 K2 K3 K4 K5 K6 K7 RCOUT
RR RC
T .G .1 T .G .2 T .G .3 T .G .4 T .G .5 T .G .6 T .G .7 T .G .8
CC
T im e r 4
Analog Switch
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HT86BXX/HT86BRXX
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. No. I/O Options 1 2 3 PA0~PA7: wake-up enable or disable (bit option) PA0~PA7: pull-high enable or disable (bit option) PB0~PB7: pull-high enable or disable (bit option) - the HT86B03 device only has PB4~PB7 HT86B03/HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30 Options
Oscillation Option 4 OSC type selection: RC or crystal
Interrupt Option 5 INT Triggering edge: Falling or both
Watchdog Options 6 7 8 WDT: enable or disable WDT clock source: WDROSC or T1 CLRWDT instructions: 1 or 2 instructions
Low Voltage Reset Option 9 LVR select: enable or disable
No. I/O Options 1 2 3 4 5 6
HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90 Options
PA0~PA7: wake-up enable or disable PA0~PA7: pull-high enable or disable PB0~PB7: pull-high enable or disable PD0~PD7: pull-high enable or disable PB share pin select: PB0~7 or K0~7 PD share pin select: PD4~7 or external RC oscillation converter pin
Oscillation Option 7 OSC type selection: RC or crystal
Interrupt Option 8 INT Triggering edge: Falling or both
Watchdog Options 9 10 11 WDT: enable or disable WDT clock source: WDROSC or T1 CLRWDT instructions: 1 or 2 instructions
Low Voltage Reset Option 12 LVR select: enable or disable
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HT86BXX/HT86BRXX
Application Circuits
HT86B03
V
DD
T r a n s is to r O u tp u t V
DD
10W 0 .1 m F 47mF
0 .1 m F
SPK (8 W /1 6 W ) 8050 R2
VDDA OSC2
AUD
R1
V
DD
OSC1 VDD R PA0~PA7 RES PB4~PB7
OSC
100mF
P o w e r A m p lifie r O u tp u t 100kW
CE 5 AUD 0 .1 m F 2 3 A u d io In 1 OUTN VDD 8
SPK (8 W /1 6 W )
V
DD
0 .1 m F
V
DD
AUD VSS VSSA
H T82V733 VREF NC
47mF 4
IN T
10mF
6
OUTP 7
H T86B 03
V
DD
10W 0 .1 m F 47mF
VDDA OSC2 4M H z~ 8M H z
V
DD
OSC1 VDD PA0~PA7 PB4~PB7 RES
100mF
100kW
0 .1 m F
V
DD
AUD VSS VSSA IN T
H T86B 03
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HT86BXX/HT86BRXX
HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30
T r a n s is to r O u tp u t V
V
DD
DD
10W 0 .1 m F 47mF
0 .1 m F
SPK (8 W /1 6 W ) 8050 R2
VDDA
VDDP OSC2
AUD
R1
V
DD
OSC1 VDD R PA0~PA7 RES PB0~PB7
OSC
100mF
P o w e r A m p lifie r O u tp u t 100kW
CE 5 AUD 0 .1 m F 2 3 A u d io In 1 OUTN VDD 8
SPK (8 W /1 6 W )
V
DD
0 .1 m F
V
DD
AUD VSS VSSA VSSP
H T82V733 VREF NC
47mF 4
IN T
10mF
6
OUTP 7
H T 8 6 B 1 0 /H T 8 6 B R 1 0 H T 8 6 B 2 0 /H T 8 6 B 3 0 /H T 8 6 B R 3 0 V
DD
47mF
VDDA
VDDP OSC2 4M H z~ 8M H z
V
DD
OSC1 VDD PA0~PA7 PB0~PB7 RES VSS VSSA VSSP
100mF
100kW
0 .1 m F
V
DD
IN T
PW M1 PW M2
SPK (8 W /1 6 W )
H T 8 6 B 1 0 /H T 8 6 B R 1 0 H T 8 6 B 2 0 /H T 8 6 B 3 0 /H T 8 6 B R 3 0 N o te : T h e P W M a p p lic a tio n r e fe r to th e d e s c r ip tio n o f P u ls e W id th M o d u la tio n O u tp u t.
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March 12, 2010
HT86BXX/HT86BRXX
HT86B40/HT86B50/HT86B60/HT86BR60
T r a n s is to r O u tp u t V
V
DD
DD
10W 0 .1 m F 47mF
0 .1 m F
SPK (8 W /1 6 W ) 8050 R2
VDDA
VDDP OSC2
AUD
R1
V
DD
OSC1 VDD R
OSC
100mF
P o w e r A m p lifie r O u tp u t 100kW RES PA0~PA7 PB0~PB7 PD4~PD 7 AUD
CE 5 AUD 0 .1 m F 2 3 10mF A u d io In 1 OUTN VDD 8
SPK (8 W /1 6 W )
V
DD
0 .1 m F
V
DD
IN T
VSS VSSA VSSP
H T82V733 VREF NC
47mF 4
6
OUTP 7
H T 8 6 B 4 0 /H T 8 6 B 5 0 /H T 8 6 B 6 0 /H T 8 6 B R 6 0
V
DD
47mF
VDDA
VDDP OSC2 4M H z~ 8M H z
V
DD
OSC1 VDD PA0~PA7 PB0~PB7 PD4~PD 7 RES
DD
100mF
100kW
0 .1 m F
V
VSS VSSA VSSP
IN T
PW M1 PW M2
SPK (8 W /1 6 W )
H T 8 6 B 4 0 /H T 8 6 B 5 0 /H T 8 6 B 6 0 /H T 8 6 B R 6 0 N o te : T h e P W M a p p lic a tio n r e fe r to th e d e s c r ip tio n o f P u ls e W id th M o d u la tio n O u tp u t.
Rev. 1.80
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March 12, 2010
HT86BXX/HT86BRXX
HT86B70/HT86B80/HT86B90
T r a n s is to r O u tp u t V
V
DD
DD
10W 0 .1 m F 47mF
0 .1 m F
SPK (8 W /1 6 W ) 8050 R2
VDDA
VDDP OSC2
AUD
R1
V
DD
OSC1 VDD R PA0~PA7 RES PB0~PB7 PD0~PD 7 AUD
OSC
100mF
P o w e r A m p lifie r O u tp u t 100kW
CE 5 AUD 0 .1 m F 2 3 10mF A u d io In 1 OUTN VDD 8
SPK (8 W /1 6 W )
V
DD
0 .1 m F
V
DD
IN T
VSS VSSA VSSP
H T82V733 VREF NC
47mF 4
6
OUTP 7
H T 8 6 B 7 0 /H T 8 6 B 8 0 /H T 8 6 B 9 0
V
DD
47mF
VDDA
VDDP OSC2 4M H z~ 8M H z
V
DD
OSC1 VDD PA0~PA7 PB0~PB7 PD0~PD 7 RES
DD
100mF
100kW
0 .1 m F
V
VSS VSSA VSSP
IN T
PW M1 PW M2
SPK (8 W /1 6 W )
H T 8 6 B 7 0 /H T 8 6 B 8 0 /H T 8 6 B 9 0 N o te : T h e P W M a p p lic a tio n r e fe r to th e d e s c r ip tio n o f P u ls e W id th M o d u la tio n O u tp u t.
Rev. 1.80
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HT86BXX/HT86BRXX
Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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HT86BXX/HT86BRXX
Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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HT86BXX/HT86BRXX
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.80
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HT86BXX/HT86BRXX
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.80 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 66 March 12, 2010
HT86BXX/HT86BRXX
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.80
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HT86BXX/HT86BRXX
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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HT86BXX/HT86BRXX
INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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HT86BXX/HT86BRXX
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
24-pin SSOP (150mil) Outline Dimensions
24 A
13 B
1
12
C C' G H D E F
a
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.335 0.054 3/4 0.004 0.022 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.20 8.51 1.37 3/4 0.10 0.56 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.30 8.79 1.52 3/4 0.25 0.71 0.25 8 Max. 0.244 0.157 0.012 0.346 0.060 3/4 0.010 0.028 0.010 8
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HT86BXX/HT86BRXX
24-pin SSOP (209mil) Outline Dimensions
24 A
13 B
1
12
C C' G H D E F
a
* MO-150
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.291 0.197 0.009 0.311 3/4 3/4 0.002 0.022 0.004 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.026 3/4 3/4 3/4 3/4 Dimensions in mm Min. 7.40 5.00 0.22 7.90 3/4 3/4 0.05 0.55 0.09 0 0.65 3/4 3/4 3/4 3/4 Nom. 3/4 3/4 3/4 3/4 Max. 8.20 5.60 0.33 8.50 2.00 3/4 3/4 0.95 0.21 8 Max. 0.323 0.220 0.013 0.335 0.079 3/4 3/4 0.037 0.008 8
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HT86BXX/HT86BRXX
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
* MS-013
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.393 0.256 0.012 0.697 3/4 3/4 0.004 0.016 0.008 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.050 3/4 3/4 3/4 3/4 Dimensions in mm Min. 9.98 6.50 0.30 17.70 3/4 3/4 0.10 0.41 0.20 0 Nom. 3/4 3/4 3/4 3/4 3/4 1.27 3/4 3/4 3/4 3/4 Max. 10.64 7.62 0.51 18.11 2.64 3/4 0.30 1.27 0.33 8 Max. 0.419 0.300 0.020 0.713 0.104 3/4 0.012 0.050 0.013 8
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HT86BXX/HT86BRXX
44-pin QFP (10mm10mm) Outline Dimensions
C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H
Symbol A B C D E F G H I J K L a Symbol A B C D E F G H I J K L a
Dimensions in inch Min. 0.512 0.390 0.512 0.390 3/4 3/4 0.075 3/4 0.010 0.029 0.004 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.031 0.012 3/4 3/4 3/4 3/4 3/4 0.004 3/4 Dimensions in mm Min. 13.00 9.90 13.00 9.90 3/4 3/4 1.90 3/4 0.25 0.73 0.10 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.80 0.30 3/4 3/4 3/4 3/4 3/4 0.10 3/4 Max. 13.40 10.10 13.40 10.10 3/4 3/4 2.20 2.70 0.50 0.93 0.20 3/4 7 Max. 0.528 0.398 0.528 0.398 3/4 3/4 0.087 0.106 0.020 0.037 0.008 3/4 7
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HT86BXX/HT86BRXX
100-pin QFP (14mm20mm) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a
Dimensions in inch Min. 0.728 0.547 0.965 0.783 3/4 3/4 0.098 3/4 3/4 0.039 0.004 0 Nom. 3/4 3/4 3/4 3/4 0.026 0.012 3/4 3/4 0.004 3/4 3/4 3/4 Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1.00 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.1 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7 Max. 0.756 0.555 0.992 0.791 3/4 3/4 0.122 0.134 3/4 0.055 0.008 7
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HT86BXX/HT86BRXX
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 24S (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 16.8
+0.3/-0.2
22.20.2
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 24.8
+0.3/-0.2
30.20.2
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Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P A0
K0
R e e l H o le p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . IC
SSOP 24S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 16.0
+0.3/-0.1
8.00.1 1.750.10 7.50.1 1.5 1.5
+0.1/-0.0 +0.25/-0.0
4.00.1 2.00.1 6.50.1 9.50.1 2.10.1 0.300.05 13.30.1
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.10 11.50.1 1.5 1.5
+0.1/-0.0 +0.25/-0.0
4.00.1 2.00.1 10.850.10 18.340.10 2.970.10 0.350.01 21.30.1
Rev. 1.80
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HT86BXX/HT86BRXX
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.80
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March 12, 2010

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